论文标题
旨在嵌入式系统的多值逻辑电路设计和数据传输
Multiple-Valued Logic Circuit Design and Data Transmission Intended for Embedded Systems
论文作者
论文摘要
本文提出了新的三元电路，旨在减少能量以保持电池消耗。拟议的设计包括八个三元逻辑门，三个三元组合电路和六个三元算术逻辑单元。本论文在减少使用的晶体管数量，利用节能晶体管布置（例如传输门）之间以及应用双电源电压来实现其目标之间采用了最佳的权衡。将所提出的设计与使用HSPICE模拟器的最新三元电路进行了比较，用于不同的供应电压，不同的温度和不同的频率。进行仿真以证明所提出的设计的效率。结果证明了拟议设计的优势，在THA的晶体管计数方面降低了73％，STI，TNAND，TDECODER，TDECODER，TMUX，THA和TMUL的能源消耗分别超过88％。此外，研究了研究主要过程变化，TOX，CNT直径，CNT计数和通道长度的噪声免疫曲线和蒙特卡洛分析。
This thesis proposes novel ternary circuits aiming to reduce energy to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units. This thesis applies the best tradeoff between reducing the number of used transistors, utilizing energy efficient transistor arrangements such as transmission gates, and applying the dual supply voltages to achieve its objective. The proposed designs are compared to the latest ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. Simulations are performed to prove the efficiency of the proposed designs. The results demonstrate the advantage of the proposed designs with a reduction of over 73 percent in terms of transistor count for the THA and over 88 percent in energy consumption for the STI, TNAND, TDecoder, TMUX, THA, and TMUL, respectively. Moreover, the noise immunity curve and Monte Carlo analysis for major process variations, TOX, CNT Diameter, CNT Count, and Channel length, were studied.
