论文标题
超快速HPSOC ASIC的反阻抗放大器阶段的首次测试结果
First Test Results of the Trans-Impedance Amplifier Stage of the Ultra-fast HPSoC ASIC
论文作者
论文摘要
我们介绍了用于读取超快速硅探测器的HPSOC ASIC的第一个结果。 TSMC在65 nm CMO中生产的4通道ASIC已针对50 UM厚的AC-LGAD进行了优化。用\ b {eta} - 粒子对模拟前端进行评估，这些粒子撞击了3x3 ac-lgad阵列（500 um螺距，200x200 um2金属）证实，快速输出的上升时间为600 ps，良好的计时性能良好，抖动为45 ps。进一步的校准实验和TCT激光研究表明，正在研究的一些增益局限性，并正在推动第二代前放大阶段的设计，以达到15 ps的抖动。
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with \b{eta}-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplification stages to reach a jitter of 15 ps.
