论文标题
概述和研究3D-TSV互连诱导的CMOS电路耦合
Overview and study of the 3D-TSV interconnects induced coupling in CMOS circuits
论文作者
论文摘要
半导体行业的快速进步将传统的二维技术推向了扩展，性能和成本因素的最大限制。这些挑战推动了3D技术在生产各种集成电路中的使用。 3D集成的众多特征之一是通过硅VIA（TSV）将多层组装到单个堆栈中。此过程最初是为记忆芯片开发的，此后已在其他微电子学领域的许多应用中使用。这项研究的目的是评估3D-TSV互连对MOS晶体管和CMOS电路性能的影响。这是使用能够描述TSV在电路级别诱导的底物耦合的数值和分析模型来完成的。分析方法提出的不仅可以研究和优化性能，不仅是MOS设备，而且还可以通过3D互连的大型CMOS电路作为各种技术和电气参数的函数。
The semiconductor industry's rapid advancement pushes conventional two-dimensional technology to its utmost limitations in terms of scaling, performance, and cost factors. These challenges drive the usage of 3D technology in the production of various Integrated Circuits. One of the numerous features of 3D Integration is the use of Through Silicon Vias (TSVs) for the assembly of multilayers into a single stack. This process, which was initially developed for memory chips, has been used afterward in many applications in other areas of microelectronics. The purpose of this research is to assess the effect of 3D-TSV interconnection on the performance of MOS transistors and CMOS circuits. This is accomplished using numerical and analytical models capable of describing the substrate coupling induced by TSV at the circuit level. The analytical approach proposed enables the study and optimization of the performance, not only of MOS devices but also large CMOS circuits with 3D interconnects as a function of various technological and electrical parameters.
