论文标题
一种基于FPGA的自动化框架，用于快速的非二进制LDPC代码
An Automated FPGA-based Framework for Rapid Prototyping of Nonbinary LDPC Codes
论文作者
论文摘要
非二元LDPC代码已显示出接近香农限制的卓越性能。与相似长度的二元LDPC代码相比，它们可以达到较低的错误率。但是，非二元LDPC代码的众多设计自由使实用的代码和解码器设计过程变得复杂。快速模拟对于评估利弊至关重要。 FPGA上的快速原型制作很有吸引力，但由于其高设计复杂性而进行了重大的设计工作。我们建议使用解码器和外围共同设计的高通量可重新配置的硬件仿真体系结构。该体系结构实现了一个基于库和脚本的框架，该框架可以自动化FPGA仿真的构建。代码和解码器设计参数是在运行时间或设计时间内通过脚本编程的。 We demonstrate the capability of the framework in evaluating practical code and decoder design by experimenting with two popular nonbinary LDPC codes, regular (2, dc) codes and quasi-cyclic codes: each emulation model can be auto-constructed within hours and the decoder delivers excellent error-correcting performance on a Xilinx Virtex-5 FPGA with throughput of up to hundreds of Mbps.
Nonbinary LDPC codes have shown superior performance close to the Shannon limit. Compared to binary LDPC codes of similar lengths, they can reach orders of magnitudes lower error rate. However, multitude of design freedoms of nonbinary LDPC codes complicates the practical code and decoder design process. Fast simulations are critically important to evaluate the pros and cons. Rapid prototyping on FPGA is attractive but takes significant design efforts due to its high design complexity. We propose a high-throughput reconfigurable hardware emulation architecture with decoder and peripheral co-design. The architecture enables a library and script-based framework that automates the construction of FPGA emulations. Code and decoder design parameters are programmed either during run time or by script in design time. We demonstrate the capability of the framework in evaluating practical code and decoder design by experimenting with two popular nonbinary LDPC codes, regular (2, dc) codes and quasi-cyclic codes: each emulation model can be auto-constructed within hours and the decoder delivers excellent error-correcting performance on a Xilinx Virtex-5 FPGA with throughput of up to hundreds of Mbps.
