论文标题
门水平传播分析的统一模型
A Unified Model for Gate Level Propagation Analysis
论文作者
论文摘要
经典的硬件验证技术（例如X-Propagation和故障传播）以及基于信息流跟踪（IFT）的最新硬件安全验证技术旨在了解信息如何传递，影响和以其他方式修改电路。这些技术都具有单独的用法方案，但是当剖析到其核心功能时，它们以基本的方式联系起来。在本文中，我们为门水平传播分析开发了一个共同的框架。我们使用我们的模型生成可综合的传播逻辑，以在标准EDA工具中使用。为了证明我们的模型是合理的，我们证明了精确的硬件IFT等同于X-Propagation和不精确的故障传播。我们还表明，精确的硬件IFT和故障传播之间的差异对于74倍序列和'85 ISCAS基准不是313个大门的'85 ISCAS基准，以及不正确的硬件IFT和精确的硬件IFT之间的差异几乎总是很重要的。
Classic hardware verification techniques (e.g., X-propagation and fault-propagation) and more recent hardware security verification techniques based on information flow tracking (IFT) aim to understand how information passes, affects, and otherwise modifies a circuit. These techniques all have separate usage scenarios, but when dissected into their core functionality, they relate in a fundamental manner. In this paper, we develop a common framework for gate level propagation analysis. We use our model to generate synthesizable propagation logic to use in standard EDA tools. To justify our model, we prove that Precise Hardware IFT is equivalent to gate level X-propagation and imprecise fault propagation. We also show that the difference between Precise Hardware IFT and fault propagation is not significant for 74X-series and '85 ISCAS benchmarks with more than 313 gates and the difference between imprecise hardware IFT and Precise Hardware IFT is almost always significant regardless of size.
