论文标题
一个用于高性能非芯片交流的开源平台
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
论文作者
论文摘要
片上沟通基础设施是现代芯片（SOCS）的核心组成部分，随着核心的数量，组件的异质性以及芯片和芯片外放宽的数量，它继续变得重要。数十年来对片上网络的研究启用了高速缓存共享内存多处理器。但是，满足异类多核和加速器丰富的SOC的需求的沟通织物（或不仅部分相干）是一个不那么成熟的研究领域。 在这项工作中，我们提出了一个模块化的，拓扑的敏锐性，高性能的片上通信平台。该平台包括用于构建和链接子网络具有可自定义带宽和并发属性的组件，并遵守最先进的行业标准协议。我们讨论了模块的微构造权衡以及定时/区域特征，并表明它们可以构建高频带（例如2.5 GHz和1024位数据宽度）端到端芯片交流面料（不仅是DMA发动机和存储器控制器，而且还具有较高的相关度）。我们设计和实施了最先进的ML培训加速器，我们的通信结构在模具上缩放到1024个内核，在任何两个内核之间仅24 ns往返潜伏期，在仅24 ns的往返延迟下提供32 TB/S横截面带宽。
On-chip communication infrastructure is a central component of modern systems-on-chip (SoCs), and it continues to gain importance as the number of cores, the heterogeneity of components, and the on-chip and off-chip bandwidth continue to grow. Decades of research on on-chip networks enabled cache-coherent shared-memory multiprocessors. However, communication fabrics that meet the needs of heterogeneous many-cores and accelerator-rich SoCs, which are not, or only partially, coherent, are a much less mature research area. In this work, we present a modular, topology-agnostic, high-performance on-chip communication platform. The platform includes components to build and link subnetworks with customizable bandwidth and concurrency properties and adheres to a state-of-the-art, industry-standard protocol. We discuss microarchitectural trade-offs and timing/area characteristics of our modules and show that they can be composed to build high-bandwidth (e.g., 2.5 GHz and 1024 bit data width) end-to-end on-chip communication fabrics (not only network switches but also DMA engines and memory controllers) with high degrees of concurrency. We design and implement a state-of-the-art ML training accelerator, where our communication fabric scales to 1024 cores on a die, providing 32 TB/s cross-sectional bandwidth at only 24 ns round-trip latency between any two cores.
