论文标题
预测过程设计套件For15 nm finfets：freepdk15
Development of a Predictive Process Design kit for15-nm FinFETs: FreePDK15
论文作者
论文摘要
预计FinFET可以推进低20nm设备的半导体标准。为了支持他们对研究和大学的介绍，开发肛门源预测过程设计套件至关重要。本文讨论了15nm FinfetDevices的此类套件的设计过程，称为Freepdk15。该套件由一个基于ASIC架构，中间的本地互连器和一组前端层层的Layerstack组成，该套件具有13米的层。定义了这些层的物理和地球分析特性，并确定设计的密度和寄生虫。考虑到其他准则可变性的其他准则，FinFET制造涉及的挑战和一组独特的设计规则是为关键维度开发的。划线提取包括修改规则，用于确定FinFET布局的地面特征，并讨论了为了获得一套成功的布局对布局的布局，并且为一个布局的布置进行了讨论。此外，分析了标准FinFET设备的其他寄生虫分数，并执行样品布局的寄生提取。然后，将其比较结果进行比较和评估，并根据验证模型进行评估。
FinFETs are predicted to advance semiconductorscaling for sub-20nm devices. In order to support their intro-duction into research and universities it is crucial to develop anopen source predictive process design kit. This paper discussesin detail the design process for such a kit for 15nm FinFETdevices, called the FreePDK15. The kit consists of a layerstack with thirteen-metal layers based on hierarchical-scalingused in ASIC architecture, Middle-of-Line local interconnectlayers and a set of Front-End-of-Line layers. The physical andgeometrical properties of these layers are defined and theseproperties determine the density and parasitics of the design. Thedesign rules are laid down considering additional guidelines forprocess variability, challenges involved in FinFET fabrication anda unique set of design rules are developed for critical dimensions.Layout extraction including modified rules for determining thegeometrical characteristics of FinFET layouts are implementedand discussed to obtain successful Layout Versus Schematicchecks for a set of layouts. Moreover, additional parasiticcomponents of a standard FinFET device are analyzed andthe parasitic extraction of sample layouts is performed. Theseextraction results are then compared and assessed against thevalidation models.
