论文标题

联锁:相互关联的逻辑和路由锁定

InterLock: An Intercorrelated Logic and Routing Locking

论文作者

Kamali, Hadi Mardani, Azar, Kimia Zamiri, Homayoun, Houman, Sasan, Avesta

论文摘要

在本文中,我们提出了一项规范的临作 - SAT(CP&SAT)攻击,以破坏基于最新的路由的混淆技术。在CP&SAT攻击中,我们首先根据适用于详细路由约束的有效的SAT编码机制编码关键程序可编程的路由块(KEYRB),然后有效地重新编码并减少使用有限的变量添加(BVA)algorithm对应于KeyRB的CNF。在CP&SAT攻击中,这是在将电路进行SAT攻击之前完成的。我们说明,基于编码和BVA的预处理大大降低了CNF的大小,对应于基于路由的混淆电路,结果我们观察到打破先前的基于ART路由的肥胖技术的100%成功率。此外,我们提出了一种新的相互关联的逻辑和路由锁定技术,或简短的互锁,以减轻CP和SAT攻击。在Interlock中,除了隐藏连接性外,在KEYRB(S)中还实现了所选正时路径中逻辑(门)的一部分。我们说明,当逻辑门与键Rbs扭曲时,BVA无法提供任何优势作为预处理步骤。我们的实验结果表明,通过使用Interlock,只有三个8 $ \ $ 8或仅两个16x16 KEYRB(与实际逻辑门扭曲),对现有攻击的弹性以及我们的新提议的CP和SAT攻击将得到保证,而平均而言,平均而言,延迟/面积的延迟/面积为中等尺寸的基础基础级别的延迟/面积小于10%。

In this paper, we propose a canonical prune-and-SAT (CP&SAT) attack for breaking state-of-the-art routing-based obfuscation techniques. In the CP&SAT attack, we first encode the key-programmable routing blocks (keyRBs) based on an efficient SAT encoding mechanism suited for detailed routing constraints, and then efficiently re-encode and reduce the CNF corresponded to the keyRB using a bounded variable addition (BVA) algorithm. In the CP&SAT attack, this is done before subjecting the circuit to the SAT attack. We illustrate that this encoding and BVA-based pre-processing significantly reduces the size of the CNF corresponded to the routing-based obfuscated circuit, in the result of which we observe 100% success rate for breaking prior art routing-based obfuscation techniques. Further, we propose a new intercorrelated logic and routing locking technique, or in short InterLock, as a countermeasure to mitigate the CP&SAT attack. In Interlock, in addition to hiding the connectivity, a part of the logic (gates) in the selected timing paths are also implemented in the keyRB(s). We illustrate that when the logic gates are twisted with keyRBs, the BVA could not provide any advantage as a pre-processing step. Our experimental results show that, by using InterLock, with only three 8$\times$8 or only two 16x16 keyRBs (twisted with actual logic gates), the resilience against existing attacks as well as our new proposed CP&SAT attack would be guaranteed while, on average, the delay/area overhead is less than 10% for even medium-size benchmark circuits.

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