论文标题
一种合奏学习方法，用于原位监视FPGA动态力量
An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power
论文作者
论文摘要
随着现场编程的门阵列在关键应用域中普遍存在，其功耗引起了人们的关注。在本文中，我们介绍并评估了能够在细粒度的时间范围内准确估算FPGA的运行时动态功率的功率监控方案，以支持新兴的电源管理技术。特别是，我们描述了一个新颖而专业的集合模型，可以将其分解为多个基于决策的基础学习者。为了帮助模型合成，提出了一种通用的计算机辅助设计流，以生成样品，选择功能，调整超参数并训练集成估计器。除此之外，还提出了训练有素的集合估算器的硬件实现，以实现实时启动估算。在实验中，我们首先表明，单个决策树模型可以在商业门级功率估计工具的4.51％以内达到预测误差，该误差比常用线性模型所提供的2.41---6.07倍。更重要的是，我们使用拟议的集合模型研究了推理准确性的额外提高。实验结果表明，整体监控方法可以进一步提高功率预测的准确性，以在最大误差1.90％以内。此外，使用多达64个基本学习者的集合监控硬件的查找表（LUT）开销占目标FPGA的1.22％以内，表明其轻巧且可扩展的特性。
As field-programmable gate arrays become prevalent in critical application domains, their power consumption is of high concern. In this paper, we present and evaluate a power monitoring scheme capable of accurately estimating the runtime dynamic power of FPGAs in a fine-grained timescale, in order to support emerging power management techniques. In particular, we describe a novel and specialized ensemble model which can be decomposed into multiple customized decision-tree-based base learners. To aid in model synthesis, a generic computer-aided design flow is proposed to generate samples, select features, tune hyperparameters and train the ensemble estimator. Besides this, a hardware realization of the trained ensemble estimator is presented for on-chip real-time power estimation. In the experiments, we first show that a single decision tree model can achieve prediction error within 4.51% of a commercial gate-level power estimation tool, which is 2.41--6.07x lower than provided by the commonly used linear model. More importantly, we study the extra gains in inference accuracy using the proposed ensemble model. Experimental results reveal that the ensemble monitoring method can further improve the accuracy of power predictions to within a maximum error of 1.90%. Moreover, the lookup table (LUT) overhead of the ensemble monitoring hardware employing up to 64 base learners is within 1.22% of the target FPGA, indicating its light-weight and scalable characteristics.
