论文标题
位平行6T SRAM使用可重构的位精确计算
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision
论文作者
论文摘要
本文介绍了基于6T SRAM单元格的基于位置内存计算（IMC）体系结构，以支持具有可重构的位精确的各种计算。在提出的技术中，比特线计算是用短的WL进行的，然后是BL增强电路，这可以减少BL计算延迟。通过在每个接近内存的电路之间执行随身携带的传播，还可以通过低延迟的迭代操作来实现位平行的复杂计算。此外，还基于携带范围的大小支持可重构的比特精确。我们的128KB内/接近内存计算体系结构已使用28nm CMOS流程实现，并且可以在1.0V时达到2.25GHz时钟频率，而面积为5.2％。所提出的体系结构也分别为平行添加和乘法达到0.68、8.09的顶部/w。此外，拟议的工作还支持从0.6V到1.1V的广泛供应电压。
This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL followed by BL boosting circuits, which can reduce BL computing delays. By performing carry-propagation between each near-memory circuit, bit-parallel complex computations are also enabled by iterating operations with low latency. In addition, reconfigurable bit-precision is also supported based on carry-propagation size. Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 1.0V with 5.2% of area overhead. The proposed architecture also achieves 0.68, 8.09 TOPS/W for the parallel addition and multiplication, respectively. In addition, the proposed work also supports a wide range of supply voltage, from 0.6V to 1.1V.
