论文标题
3D逻辑单元格设计和基于垂直NWFET技术的结果，包括绑定紧凑的模型
3D logic cells design and results based on Vertical NWFET technology including tied compact model
论文作者
论文摘要
全面的垂直纳米线场效应晶体管（VNWFET）是新兴的设备，非常适合追求超出7nm左右的横向缩放限制。这项工作探讨了逻辑细胞设计背景下该技术的相对优点和缺点。我们描述了一种无连接的纳米线技术和相关的紧凑模型，该模型可以准确地描述了晶体管所有操作中的制造设备行为，该模型基于22至50nm之间的16至625个平行纳米线。我们使用此模型来模拟基于被动负载，主动载荷和互补拓扑的逆变器逻辑门的预计性能，并对晶体管中纳米线的数量进行性能探索。在紧凑性方面，通过专用的完整3D布局设计，我们还证明了相对于基于7nm FinFET的逆变器，互补结构的横向尺寸降低了1.4倍。
Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and carry out an performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 1.4x reduction in lateral dimensions for the complementary structure with respect to 7nm FinFET-based inverters.
