论文标题
基于FPGA的神经形态架构的仿真环境
FPGA Based Emulation Environment for Neuromorphic Architectures
论文作者
论文摘要
已经引入了诸如IBM的Truenorth和Intel的Loihi之类的神经形态体系结构,作为节能尖峰神经网络执行的平台。但是,没有框架可以快速尝试使用神经形态体系结构并研究硬件性能和网络准确性的贸易空间。从根本上讲,这为希望探索神经形态体系结构的硬件设计师的入境障碍造成了障碍。在本文中,我们为神经形态计算研究提供了基于FPGA的开源仿真环境。我们原型IBM的Truenorth体系结构是参考设计,并讨论实施和集成其核心组件时做出的FPGA特定设计决策。我们进行资源利用分析,并在Zynq Ultrascale+ MPSOC上实现启用流媒体的Truenorth架构。然后,我们通过在仿真环境中实现MNIST数据集和向量矩阵乘法(VMM)的网络来执行功能验证,并根据使用IBM的Compass Simulation环境生成的相同网络进行基于精度的比较。我们通过更改VMM映射的神经元行为来证明仿真环境对硬件设计师和应用程序工程师的实用性,据我们所知,对于包括IBM的Compass环境在内的任何其他工具,这是不可行的。提议的参数化和可配置的仿真平台是扩展其功能以支持新兴体系结构,研究假设的神经形态架构的基础,或在应用程序映射过程中显而易见,通过基于瓶颈变得显而易见,通过增量更改通过增量变化而迅速融合到硬件配置。
Neuromorphic architectures such as IBM's TrueNorth and Intel's Loihi have been introduced as platforms for energy efficient spiking neural network execution. However, there is no framework that allows for rapidly experimenting with neuromorphic architectures and studying the trade space on hardware performance and network accuracy. Fundamentally, this creates a barrier to entry for hardware designers looking to explore neuromorphic architectures. In this paper we present an open-source FPGA based emulation environment for neuromorphic computing research. We prototype IBM's TrueNorth architecture as a reference design and discuss FPGA specific design decisions made when implementing and integrating it's core components. We conduct resource utilization analysis and realize a streaming-enabled TrueNorth architecture on the Zynq UltraScale+ MPSoC. We then perform functional verification by implementing networks for MNIST dataset and vector matrix multiplication (VMM) in our emulation environment and present an accuracy-based comparison based on the same networks generated using IBM's Compass simulation environment. We demonstrate the utility of our emulation environment for hardware designers and application engineers by altering the neuron behavior for VMM mapping, which is, to the best of our knowledge, not feasible with any other tool including IBM's Compass environment. The proposed parameterized and configurable emulation platform serves as a basis for expanding its features to support emerging architectures, studying hypothetical neuromorphic architectures, or rapidly converging to hardware configuration through incremental changes based on bottlenecks as they become apparent during application mapping process.